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Microarchitectural Wire Management for Performance and Power in Partitioned Architectures

Invention Summary: Chip multi-processors (CMPs) containing multiple cores, each with an associated cache, require a cache coherence protocol within the chip. With different threads of a multi-threaded (or parallel) program executing on different cores, cache coherence is a key contributor to performance and overall processor power. Wires in the...

Published: 5/14/2019 | Inventor(s): Liqun Cheng, Naveen Muralimanohar, Karthik Ramani, Rajeev Balasubramonian, John Carter

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Category(s): Hardware, Circuits & Sensors, Semiconductors